diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index a77a68d..cdadd38 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -199,7 +199,8 @@
 	default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
 	default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
 	default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
-	default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3
+	default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
+	default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
 	default 0x680000 if SYS_LS_PPA_FW_IN_MMC
 	default 0x680000 if SYS_LS_PPA_FW_IN_NAND
 	help
diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h
index 63845a2..ec6463d 100644
--- a/arch/arm/include/asm/fsl_secure_boot.h
+++ b/arch/arm/include/asm/fsl_secure_boot.h
@@ -72,8 +72,13 @@
  * DDR memory map
  */
 #ifdef CONFIG_FSL_LSCH3
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_BS_ADDR_DEVICE		0x20600000
+#define CONFIG_BS_HDR_ADDR_DEVICE	0x20640000
+#else /* NOR BOOT */
 #define CONFIG_BS_ADDR_DEVICE		0x580600000
 #define CONFIG_BS_HDR_ADDR_DEVICE	0x580640000
+#endif /*ifdef CONFIG_QSPI_BOOT */
 #define CONFIG_BS_SIZE			0x00001000
 #define CONFIG_BS_HDR_SIZE		0x00004000
 #define CONFIG_BS_ADDR_RAM		0xa0600000
diff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c
index 83773d0..1842d14 100644
--- a/board/freescale/ls2080aqds/ls2080aqds.c
+++ b/board/freescale/ls2080aqds/ls2080aqds.c
@@ -226,15 +226,14 @@
 #endif
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 	rtc_enable_32khz_output();
+#ifdef CONFIG_FSL_CAAM
+	sec_init();
+#endif
 
 #ifdef CONFIG_FSL_LS_PPA
 	ppa_init();
 #endif
 
-#ifdef CONFIG_FSL_CAAM
-	sec_init();
-#endif
-
 	return 0;
 }
 
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index 07ba026..666562d 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -218,6 +218,10 @@
 #ifdef CONFIG_FSL_QIXIS
 	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
 #endif
+
+#ifdef CONFIG_FSL_CAAM
+	sec_init();
+#endif
 #ifdef CONFIG_FSL_LS_PPA
 	ppa_init();
 #endif